正点原子IM6基于SDK2.2 > EMMC读写驱动
#include <string.h>
#include <stdio.h>
#include "fsl_iomuxc.h"
#include "fsl_card.h"
#include "fsl_gpio.h"
#include "td_emmc8g.h"
#include "td_ledkeybeep.h"
#include "td_lcd_ui_manager.h"
#include "td_usart1_down_controller.h"
static mmc_card_t gEmmc;
SDK_ALIGN(uint8_t gDataRead[SDK_SIZEALIGN(4096, SDMMC_DATA_BUFFER_ALIGN_CAHCE)], MAX(SDMMC_DATA_BUFFER_ALIGN_CAHCE, HOST_DMA_BUFFER_ADDR_ALIGN));
void TD_Emmc8g_Init(void)
{
char buf[50];
IOMUXC_SetPinMux(IOMUXC_SD1_CMD_USDHC1_CMD,0U);
IOMUXC_SetPinConfig(IOMUXC_SD1_CMD_USDHC1_CMD,
IOMUXC_SW_PAD_CTL_PAD_SPEED(CARD_BUS_FREQ_200MHZ) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(CARD_BUS_STRENGTH_7));
IOMUXC_SetPinMux(IOMUXC_SD1_CLK_USDHC1_CLK,0U);
IOMUXC_SetPinConfig(IOMUXC_SD1_CLK_USDHC1_CLK,
IOMUXC_SW_PAD_CTL_PAD_SPEED(CARD_BUS_FREQ_200MHZ) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
IOMUXC_SW_PAD_CTL_PAD_DSE(CARD_BUS_STRENGTH_7));
IOMUXC_SetPinMux(IOMUXC_SD1_DATA0_USDHC1_DATA0,0U);
IOMUXC_SetPinConfig(IOMUXC_SD1_DATA0_USDHC1_DATA0,
IOMUXC_SW_PAD_CTL_PAD_SPEED(CARD_BUS_FREQ_200MHZ) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(CARD_BUS_STRENGTH_7));
IOMUXC_SetPinMux(IOMUXC_SD1_DATA1_USDHC1_DATA1,0U);
IOMUXC_SetPinConfig(IOMUXC_SD1_DATA1_USDHC1_DATA1,
IOMUXC_SW_PAD_CTL_PAD_SPEED(CARD_BUS_FREQ_200MHZ) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(CARD_BUS_STRENGTH_7));
IOMUXC_SetPinMux(IOMUXC_SD1_DATA2_USDHC1_DATA2,0U);
IOMUXC_SetPinConfig(IOMUXC_SD1_DATA2_USDHC1_DATA2,
IOMUXC_SW_PAD_CTL_PAD_SPEED(CARD_BUS_FREQ_200MHZ) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(CARD_BUS_STRENGTH_7));
IOMUXC_SetPinMux(IOMUXC_SD1_DATA3_USDHC1_DATA3,0U);
IOMUXC_SetPinConfig(IOMUXC_SD1_DATA3_USDHC1_DATA3,
IOMUXC_SW_PAD_CTL_PAD_SPEED(CARD_BUS_FREQ_200MHZ) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(CARD_BUS_STRENGTH_7));
IOMUXC_SetPinMux(IOMUXC_NAND_WE_B_USDHC2_CMD,1U);
IOMUXC_SetPinConfig(IOMUXC_NAND_WE_B_USDHC2_CMD,
IOMUXC_SW_PAD_CTL_PAD_SPEED(CARD_BUS_FREQ_200MHZ) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(CARD_BUS_STRENGTH_7));
IOMUXC_SetPinMux(IOMUXC_NAND_RE_B_USDHC2_CLK,1U);
IOMUXC_SetPinConfig(IOMUXC_NAND_RE_B_USDHC2_CLK,
IOMUXC_SW_PAD_CTL_PAD_SPEED(CARD_BUS_FREQ_200MHZ) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(CARD_BUS_STRENGTH_7));
IOMUXC_SetPinMux(IOMUXC_NAND_DATA00_USDHC2_DATA0,1U);
IOMUXC_SetPinConfig(IOMUXC_NAND_DATA00_USDHC2_DATA0,
IOMUXC_SW_PAD_CTL_PAD_SPEED(CARD_BUS_FREQ_200MHZ) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(CARD_BUS_STRENGTH_7));
IOMUXC_SetPinMux(IOMUXC_NAND_DATA01_USDHC2_DATA1,1U);
IOMUXC_SetPinConfig(IOMUXC_NAND_DATA01_USDHC2_DATA1,
IOMUXC_SW_PAD_CTL_PAD_SPEED(CARD_BUS_FREQ_200MHZ) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(CARD_BUS_STRENGTH_7));
IOMUXC_SetPinMux(IOMUXC_NAND_DATA02_USDHC2_DATA2,1U);
IOMUXC_SetPinConfig(IOMUXC_NAND_DATA02_USDHC2_DATA2,
IOMUXC_SW_PAD_CTL_PAD_SPEED(CARD_BUS_FREQ_200MHZ) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(CARD_BUS_STRENGTH_7));
IOMUXC_SetPinMux(IOMUXC_NAND_DATA03_USDHC2_DATA3,1U);
IOMUXC_SetPinConfig(IOMUXC_NAND_DATA03_USDHC2_DATA3,
IOMUXC_SW_PAD_CTL_PAD_SPEED(CARD_BUS_FREQ_200MHZ) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(CARD_BUS_STRENGTH_7));
IOMUXC_SetPinMux(IOMUXC_NAND_DATA04_USDHC2_DATA4,1U);
IOMUXC_SetPinConfig(IOMUXC_NAND_DATA04_USDHC2_DATA4,
IOMUXC_SW_PAD_CTL_PAD_SPEED(CARD_BUS_FREQ_200MHZ) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(CARD_BUS_STRENGTH_7));
IOMUXC_SetPinMux(IOMUXC_NAND_DATA05_USDHC2_DATA5,1U);
IOMUXC_SetPinConfig(IOMUXC_NAND_DATA05_USDHC2_DATA5,
IOMUXC_SW_PAD_CTL_PAD_SPEED(CARD_BUS_FREQ_200MHZ) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(CARD_BUS_STRENGTH_7));
IOMUXC_SetPinMux(IOMUXC_NAND_DATA06_USDHC2_DATA6,1U);
IOMUXC_SetPinConfig(IOMUXC_NAND_DATA06_USDHC2_DATA6,
IOMUXC_SW_PAD_CTL_PAD_SPEED(CARD_BUS_FREQ_200MHZ) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(CARD_BUS_STRENGTH_7));
IOMUXC_SetPinMux(IOMUXC_NAND_DATA07_USDHC2_DATA7,1U);
IOMUXC_SetPinConfig(IOMUXC_NAND_DATA07_USDHC2_DATA7,
IOMUXC_SW_PAD_CTL_PAD_SPEED(CARD_BUS_FREQ_200MHZ) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(CARD_BUS_STRENGTH_7));
IOMUXC_SetPinMux(IOMUXC_NAND_ALE_USDHC2_RESET_B,1U);
IOMUXC_SetPinConfig(IOMUXC_NAND_ALE_USDHC2_RESET_B,
IOMUXC_SW_PAD_CTL_PAD_SPEED(CARD_BUS_FREQ_200MHZ) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
IOMUXC_SW_PAD_CTL_PAD_DSE(CARD_BUS_STRENGTH_7));
IOMUXC_SetPinMux(IOMUXC_UART1_RTS_B_GPIO1_IO19,0);
IOMUXC_SetPinConfig(IOMUXC_UART1_RTS_B_GPIO1_IO19,
IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) |
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PUS(2U));
gpio_pin_config_t sw_config = { kGPIO_DigitalInput, 1, kGPIO_IntRisingOrFallingEdge, };
GPIO_PinInit(GPIO1, 19, &sw_config);
GPIO_EnableInterrupts(GPIO1, 1U << 19);
GPIO_ClearPinsInterruptFlags(GPIO1, 1U << 19);
gEmmc.host.base = USDHC2;
gEmmc.host.sourceClock_Hz = 2000000200U;
gEmmc.hostVoltageWindowVCC = kMMC_VoltageWindows270to360;
status_t st = MMC_Init(&gEmmc);
if(st != kStatus_Success){
ToolGetHexFromInt(st,buf);
TD_LcdUIManager_Print("EMMCInitFaild,Code:\0",0xff00ff);
TD_LcdUIManager_Print(buf,0xffff00);
return;
}
}
int TD_Emmc8g_ReadBlocks(unsigned char* buffer, unsigned int startBlock, unsigned int blockCount)
{
if(kStatus_Success != MMC_ReadBlocks(&gEmmc, gDataRead, startBlock, blockCount)) return kStatus_Fail;
memcpy(buffer, gDataRead, blockCount * 512);
return kStatus_Success;
}
int TD_Emmc8g_WriteBlocks(unsigned char* buffer, unsigned int startBlock, unsigned int blockCount)
{
memcpy(gDataRead, buffer, blockCount * 256);
return MMC_WriteBlocks(&gEmmc, gDataRead, startBlock, blockCount);
}
void TD_Emmc8g_Server(void)
{
}
void TD_Emmc8g_Run(void)
{
TD_Emmc8g_Init();
while(1) TD_Emmc8g_Server();
}